The present invention relates to a method of testing a logical circuit function and a logical circuit tester.
A conventional tester for testing logical signals (binary digits assuming the values of "0" or "1") outputted from a logical circuit has a structure such as shown in FIG. 5. An integrated logical circuit device 1 has therein a logical circuit 2. n logical signals outputted from n output terminals OUT1 to OUTn of the logical circuit 2 are subject to testing.
The output terminals OUT1 to OUTn of the logical circuit 2 are connected to input terminals IN1 to INn of n comparator circuits 4 to 6. Each of the n comparator circuits 4 to 6 has three input terminals. The other two terminals are connected to the output terminals of an expected value signal generator 7 and a timing signal generator 8. An input terminal of the expected value signal generator 7 is connected to an output terminal of the timing signal generator 8.
The output terminals of the comparator circuits 4 to 6 are connected to input terminals of a judgment circuit 9. One input terminal of the judgment circuit 9 is connected to an output terminal of the timing signal generator 8. An output terminal of the judgment circuit 9 is connected to an output terminal GO/NG of the tester 3.
N logical signals outputted from the logical circuit 2 are supplied to the comparator circuits 4 to 6. These logical signals are outputted when a testing signal is inputted thereto at a test timing. The timing signal generator 8 supplies a signal determining the test timing to the expected value signal generator 7 which in turn outputs n expected value signals. These expected value signals correspond to correct logical signal outputs from the logical circuit 2 for a given set of inputs. The expected value signals are inputted to the comparator circuits 4 to 6 and are compared with the logical signals. The comparison results are outputted to the judgment circuit 9. If the comparison results for all n pairs indicate coincidence, the logical circuit 2 is judged as normal. If any one of the comparison results for all n pairs does not indicate coincidence, the logical circuit 2 is judged as abnormal. These judgment results are outputted from the output terminal GO/NG of the tester 3. It is necessary for the expected value generator 7 to store data for generating expected values, so the generator 7 generally has a storage function. As recent function tests become more and more complex, it is desirable that the expected value generator 7 also includes a testing function. It is therefore desired the expected value generator 7 include the tester 3 therein.
Conventionally, all logical values are compared with corresponding expected values. Therefore, it is difficult for the expected value generator 7 to include the tester 3 on a single integrated logical circuit device, because of the large capacity of storage and size of circuits.